1. Field of the Invention
The present invention relates generally to a data processing apparatus, and more particularly to a method and an apparatus for controlling a plurality of interruption processings in a data processing system.
2. Description of the Prior Art
An interruption control functions to temporarily stop the program processing which is being row executed by a central processing unit (which will be called the "CPU") , when the CPU must execute an urgent processing, and to cause the CPU to preferentially execute the urgent processing. In general, a plurality of interruption sources are employed in a data processing system, and through an interrupt request each source requests urgent processings by the CPU at an arbitrary timing. In a microcomputer, these interruption sources are divided into two kinds, external sources and internal sources.
The external sources are provided outside of the microcomputer chip and involve a source for making a microcomputer recognize that an external device coupled to the microcomputer chip has come into a special state, a source for indicating a processing request from an external peripheral unit to the microcomputer, and so on. On the other hand, the internal sources are provided in the microcomputer chip and involve a source for indicating a processing request from an internal peripheral unit, such as a timer or an interface unit, and so on.
When the microcomputer is coupled to a variety of interruption sources, plural sources may simultaneously request interruptions, or another interruption may be generated during a processing initiated by a previous interruption (a multiple interruption mode). For example, the interruption request from an internal timer and the interruption request from a data transfer unit may simultaneously occur, or the external interruption request may occur during the internal interruption processing. In these cases, the interruption which is to be preferentially processed must be determined quickly.
For example, in the case where an internal timer interruption request and an external interruption request simultaneously occur, and the internal interruption request signals that an external unit must be controlled on a real time basis over a designated time interval by a microcomputer generated control signal, the internal timer interruption has priority. On the other hand, when external data is to be inputted into the microcomputer at high speed by use of the external interruption, the processing of the external peripheral unit is delayed unless the external interruption has priority.
Since the priority order for interruptions in data processing systems is subject to change, the interruption control apparatus used in a data processing system must be capable of changing the priority order for interruptions. If an interruption having a higher priority occurs during the period when one interruption is being processed, the interruption control apparatus must direct execution of the interruption processing program of the higher priority.
Moreover, it is also desired to provide an interruption control by which a plurality of interruptions with the same priority level can be processed.
In the prior art, an interruption control apparatus having the aforementioned control functions needs a very complex hardware mechanism or needs many steps of software processing. The complex hardware mechanism is very expensive, and has limited system application because the priority is fixed by the hardware design. The software processing also has its limitations for a long period of time is required for interruption control using software processing.